Bio

I am an associate professor at CITIUS in University of Santiago de Compostela (Galicia, Spain). My research interests include parallel and distributed computing, Big Data technologies, programming models and software optimization techniques for emerging architectures. I received the B.Sc. in physics and the Ph.D. in computer science (2006) from University of Santiago de Compostela (Spain). I was a visiting postdoctoral researcher at University Carlos III de Madrid (Spain) and University of Illinois at Urbana-Champaign (USA), and I also worked as researcher and project manager at Galicia Supercomputing Center (Spain).

Publications

Journals

  1. SparkBWA: Speeding Up the Alignment of High-Throughput DNA Sequencing Data   
    José M. Abuín, Juan C. Pichel, Tomás F. Pena and Jorge Amigo.
    PLoS ONE, Vol. 11, Issue 5, pages 1-21, 2016.
  2. Boosting Performance of a Statistical Machine Translation System Using Dynamic Parallelism   
    M. Fernández, Juan C. Pichel, José C. Cabaleiro and Tomás F. Pena.
    Journal of Computational Science, Vol. 13, pages 37-48, 2016.
  3. BigBWA: Approaching the Burrows-Wheeler Aligner to Big Data Technologies   
    José M. Abuín, Juan C. Pichel, Tomás F. Pena and Jorge Amigo.
    Bioinformatics, Vol. 31, Issue 24, pages 4003-4005, 2015.
  4. Power and Energy Implications of the Number of Threads Used on the Intel Xeon Phi   
    Oscar G. Lorenzo, Tomás F. Pena, José C. Cabaleiro, Juan C. Pichel, F.F. Rivera and D. S. Nikolopoulos.
    Annals of Multicore and GPU Programming, Vol. 2, Issue 1, pages 55-65, 2015.
  5. Análisis Morfosintáctico y Clasificación de Entidades Nombradas en un Entorno Big Data   
    Pablo Gamallo, Juan C. Pichel, Marcos García, José M. Abuín and Tomás F. Pena.
    Procesamiento del Lenguaje Natural, Vol. 53, pages 17-24, 2014.
  6. Using an Extended Roofline Model to Understand Data and Thread Affinities on NUMA Systems   
    Oscar G. Lorenzo, Tomás F. Pena, José C. Cabaleiro, Juan C. Pichel and Francisco F. Rivera.
    Annals of Multicore and GPU Programming, Vol. 1, Issue 1, pages 56-67, 2014.
  7. A Hardware Counter-Based Toolkit for the Analysis of Memory Accesses in SMPs
    Oscar G. Lorenzo, Tomás F. Pena, José C. Cabaleiro, Juan C. Pichel, Juan A. Lorenzo and Francisco F. Rivera.
    Concurrency and Computation: Practice and Experience, Vol. 26, Issue 6, pages 1328-1341, 2014.
  8. Using Sampled Information, Is It Enough for the SpMV Locality Optimization?   
    Juan C. Pichel, Juan A. Lorenzo, Dora B. Heras, Francisco F. Rivera and Tomás F. Pena.
    Concurrency and Computation: Practice and Experience, Vol. 26, Issue 1, pages 98-117, 2014.
  9. 3DyRM: A Dynamic Roofline Model Including Memory Latency Information
    Oscar G. Lorenzo, Tomás F. Pena, Juan C. Pichel, José C. Cabaleiro and Francisco F. Rivera.
    Journal of Supercomputing, Vol. 70, Issue 2, pages 696-708, 2014.
  10. Sparse Matrix–Vector Multiplication on the Single-Chip Cloud Computer Many-Core Processor   
    Juan C. Pichel and Francisco F. Rivera.
    Journal of Parallel and Distributed Computing, Vol. 73, Issue 12, pages 1539-1550, 2013.
  11. A Flexible and Dynamic Page Migration Infrastructure Based on Hardware Counters   
    Juan A. Lorenzo, Juan C. Pichel, Francisco F. Rivera, Jose C. Cabaleiro and Tomás F. Pena.
    Journal of Supercomputing, Vol. 65, Issue 2, pages 930-948, 2013.
  12. Optimization of Sparse Matrix-Vector Multiplication Using Reordering Techniques on GPUs   
    Juan C. Pichel, Francisco F. Rivera, Marcos Fernández and Aurelio Rodríguez.
    Microprocessors and Microsystems, Vol. 36, Issue 2, pages 65-77, 2012.
  13. Analyzing the Execution of Sparse Matrix-Vector Product on the Finisterrae SMP-NUMA System
    Juan C. Pichel, Juan A. Lorenzo, Dora B. Heras, José C. Cabaleiro and Tomás F. Pena.
    Journal of Supercomputing, Vol. 58, Issue 2, pages 195-205, 2011.
  14. Increasing the Locality of Iterative Methods and its Application to the Simulation of Semiconductor Devices   
    Juan C. Pichel, Dora B. Heras, José C. Cabaleiro, A. J. Garcia-Loureiro and Francisco F. Rivera.
    Int. Journal of High Performance Computing Applications, Vol. 24, Issue 2, pages 136-153, 2010.
  15. Increasing Data Reuse of Sparse Algebra Codes on Simultaneous Multithreading Architectures   
    Juan C. Pichel, Dora B. Heras, José C. Cabaleiro and Francisco F. Rivera.
    Concurrency and Computation: Practice and Experience, Vol. 21, Issue 15, pages 1838-1856, 2009.
  16. A Collective I/O Implementation Based on Inspector-Executor Paradigm
    David E. Singh, Florin Isaila, Juan C. Pichel and Jesús Carretero.
    Journal of Supercomputing, Vol. 47, Issue 1, pages 53-75, 2009.
  17. Image Segmentation Based on Merging of Sub-Optimal Segmentations   
    Juan C. Pichel, David E. Singh and Francisco F. Rivera.
    Pattern Recognition Letters, Vol. 27, Issue 10, pages 1105-1116, 2006.
  18. Performance Optimization of Irregular Codes Based on the Combination of Reordering and Blocking Techniques   
    Juan C. Pichel, Dora B. Heras, José C. Cabaleiro and Francisco F. Rivera.
    Parallel Computing, Vol. 31, Issue 8-9, pages 858-876, 2005.

Conferences

  1. Sentiment Analysis on Multilingual Tweets using Big Data Technologies   
    Rodrigo Martínez-Castaño, Juan C. Pichel and Pablo Gamallo.
    Jornadas Sarteco (JP). Salamanca, Spain, September 2016.
  2. Power and Energy Implications of the Number of Threads Used on the Intel Xeon Phi
    Oscar G. Lorenzo, Tomás F. Pena, José C. Cabaleiro, Juan C. Pichel, F.F. Rivera and D. S. Nikolopoulos.
    2nd Congress on Multicore and GPU Programming. Cáceres, Spain, March 2015.
  3. Perldoop: Efficient Execution of Perl Scripts on Hadoop Clusters   
    José M. Abuín, Juan C. Pichel, Tomás F. Pena, Pablo Gamallo and Marcos García.
    IEEE Int. Conference on Big Data (IEEE Big Data). Washington D.C., USA, October 2014.
  4. Thread Migration Techniques Based on Dynamic Roofline Models and Latency Information
    Oscar G. Lorenzo, Tomás F. Pena, José C. Cabaleiro, Juan C. Pichel and F.F. Rivera.
    XXV Jornadas de Paralelismo. Valladolid, Spain, September 2014.
  5. Multiobjective Optimization Technique Based on Monitoring Information to Increase the Performance of Thread Migration on Multicores
    Oscar G. Lorenzo, Tomás F. Pena, José C. Cabaleiro, Juan C. Pichel and F.F. Rivera
    IEEE Int. Conference on Cluster Computing (CLUSTER). Madrid, Spain, September 2014.
  6. Hierarchically Tiled Array as a High-Level Abstraction for Codelets   
    Chih-Chieh Yang, Juan C. Pichel, Adam R. Smith and David A. Padua.
    4th Int. Workshop on Data-Flow Models for Extreme Scale Computing (DFM). Edmonton, Alberta, Canada, August 2014.
  7. DyRM: A Dynamic Roofline Model Based on Runtime Information
    Oscar G. Lorenzo, Tomás F. Pena, José C. Cabaleiro, Juan C. Pichel and Francisco F. Rivera.
    13th Int. Conference on Computational and Mathematical Methods in Science and Engineering (CMMSE). Almería, Spain, June 2013.
  8. Hardware Counters Based Analysis of Memory Accesses in SMPs
    Oscar G. Lorenzo, Tomás F. Pena, Jose C. Cabaleiro, Juan C. Pichel, Juan A. Lorenzo and Francisco F. Rivera.
    10th IEEE Int. Symposium on Parallel and Distributed Processing with Applications (ISPA). Leganés, Spain, July 2012.
  9. A Graphical Tool for Performance Analysis of Multicore Systems Based on the Roofline Model
    Francisco F. Rivera, R. Iglesias, Juan A. Lorenzo, Juan C. Pichel, Tomás F. Pena and Jose C. Cabaleiro.
    10th IEEE Int. Symposium on Parallel and Distributed Processing with Applications (ISPA). Leganés, Spain, July 2012.
  10. Experiences with the Sparse Matrix-Vector Multiplication on a Many-Core Processor      
    Juan C. Pichel and Francisco F. Rivera.
    21st Int. Heterogeneity in Computing Workshop (HCW, together with IPDPS). Shanghai, China, May 2012.
  11. Herramientas para la Monitorización de los Accesos a Memoria de Códigos Paralelos Mediante Contadores Hardware
    Oscar G. Lorenzo, Juan A. Lorenzo, Dora B. Heras, Juan C. Pichel and Francsico F. Rivera.
    XXII Jornadas de Paralelismo. La Laguna, Spain, September 2011.
  12. Study of Performance Issues on a SMP-NUMA System Using the Roofline Model
    Juan A. Lorenzo, Juan C. Pichel, Tomás F. Pena, Marcos Suarez and Francisco F. Rivera.
    Int. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA). Las Vegas, USA, July 2011.
  13. A Study of Memory Access Patterns in Irregular Parallel Codes Using Hardware Counter-Based Tools
    Oscar G. Lorenzo, Juan A. Lorenzo, José C. Cabaleiro, Dora B. Heras, Marcos Suarez, and Juan C. Pichel.
    Int. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA). Las Vegas, USA, July 2011.
  14. Lessons Learnt Porting Parallelisation Techniques for Irregular Codes to NUMA Systems   
    Juan A. Lorenzo, Juan C. Pichel, David LaFrance-Linden, Francisco F. Rivera and David E. Singh.
    18th Euromicro Conference on Parallel, Distributed and Network based Processing (PDP). Pisa, Italia, February 2010.
  15. On the Influence of Thread Allocation for Irregular Codes in NUMA Systems   
    Juan A. Lorenzo, Francisco F. Rivera, Petr Tuma and Juan C. Pichel.
    10th Int. Conf. on Parallel and Distributed Computing, Applications and Technologies (PDCAT). Hiroshima, Japan, December 2009.
  16. Thread Allocation Issues for Irregular Codes in the Finisterrae System
    Juan A. Lorenzo, Francisco F. Rivera, Dora B. Heras, José C. Cabaleiro, Tomás F. Pena, Juan C. Pichel and David E. Singh.
    XX Jornadas de Paralelismo. A Coruña, Galicia, Spain, September 2009.
  17. Evaluating Sparse Matrix-Vector Product on the FinisTerrae Supercomputer   
    Juan C. Pichel, Juan A. Lorenzo, Dora B. Heras and José C. Cabaleiro.
    9th Int. Conference on Computational and Mathematical Methods in Science and Engineering (CMMSE). Gijón, Spain, June 2009.
  18. Exploiting Data Compression in Collective I/O Techniques   
    Rosa Filgueira, David E. Singh, Juan C. Pichel and Jesús Carretero.
    IEEE Int. Conference on Cluster Computing. Tsukuba, Japan, September 2008.
  19. Reordering Algorithms for Increasing Locality on Multicore Processors   
    Juan C. Pichel, David E. Singh and Jesús Carretero.
    10th IEEE Int. Conference on High Performance Computing and Communications (HPCC). Dalian, China, September 2008.
  20. Data Locality Aware Strategy for Two-Phase Collective I/O   
    Rosa Filgueira, David E. Singh, Juan C. Pichel, Florin Isaila and Jesús Carretero.
    Int. Meeting High Performance Computing for Computational Science (VECPAR). Toulouse, France, June 2008.
  21. A Collective I/O Implementation Based on Inspector-Executor Paradigm   
    David E. Singh, Florin Isaila, Juan C. Pichel and Jesús Carretero.
    Int. Workshop on Scalable Data Management Applications and Systems (SDMAS). Las Vegas, USA, June 2007.
  22. A New Technique to Reduce False Sharing in Irregular Codes Based on Distance Functions   
    Juan C. Pichel, Dora B. Heras, José C. Cabaleiro and Francisco F. Rivera.
    8th Int. Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN). pp. 306-311. Las Vegas, USA, December 2005.
  23. Mejora de la Localidad en SMPs: el Producto Matriz Dispersa-Vector como Caso de Estudio
    Juan C. Pichel, Dora B. Heras, José C. Cabaleiro, Marcos Boullón, David E. Singh and Francsico F. Rivera.
    XV Jornadas de Paralelismo. Almería, Spain, September 2004.
  24. Improving the Locality of the Sparse Matrix-Vector product on Shared Memory Multiprocessors   
    Juan C. Pichel, Dora B. Heras, José C. Cabaleiro and Francisco F. Rivera.
    12th Euromicro Conference on Parallel, Distributed and Network based Processing (PDP). A Coruña, Galicia, February 2004.
  25. Algoritmo Paralelo de Segmentación de Imágenes Basado en el Crecimiento Desacoplado de Regiones
    Juan C. Pichel, David E. Singh and Francisco F. Rivera.
    Conferencia Iberoamericana en Sistemas, Cibernética e Informática (CISCI). pp. 134-139. Orlando, USA, July 2002.

Book chapters

  1. A Parallel Framework for Image Segmentation Using Region Based Techniques   
    Juan C. Pichel, David E. Singh and Francisco F. Rivera
    Vision Systems: Segmentation and Pattern Recognition, edited by Goro Obinata and Ashish Dutta, 2007.

Software

SparkBWA

  

SparkBWA is a new tool that exploits the capabilities of a Big Data technology as Apache Spark to boost the performance of one of the most widely adopted DNA sequence aligner, the Burrows-Wheeler Aligner (BWA).

Citation:
José M. Abuín, Juan C. Pichel, Tomás F. Pena and Jorge Amigo. SparkBWA: Speeding Up the Alignment of High-Throughput DNA Sequencing Data. PLoS ONE, Vol. 11, Issue 5, pp. 1-21, 2016.

BigBWA

  

BigBWA allows to execute the Burrows-Wheeler Aligner (BWA) on an Apache Hadoop cluster.

Citation:
José M. Abuín, Juan C. Pichel, Tomás F. Pena and Jorge Amigo. BigBWA: Approaching the Burrows-Wheeler Aligner to Big Data Technologies. Bioinformatics, Vol. 31, Issue 24, pp. 4003-4005, 2015.

Perldoop

  

Perldoop automatically translates Hadoop-ready Perl scripts into its Java counterparts, which can be directly executed on a Hadoop cluster while improving their performance significantly.

Citation:
José M. Abuín, Juan C. Pichel, Tomás F. Pena, Pablo Gamallo and Marcos García. Perldoop: Efficient Execution of Perl Scripts on Hadoop Clusters. IEEE Int. Conference on Big Data (IEEE Big Data), pp. 766-771, 2014.

Projects

Here you can find a list of some of the most relevant research projects I am/was involved with:

BigNLP: Approaching High Performance Computing to Big Data Technologies: Natural Language Processing as Case Study
Funded by Ministerio de Economía y Competitividad (TIN2014-54565-JIN)
Period: Sep 2015 - Sep 2018
HPCNLP: High Performance Computing for Natural Language Processing   
Funded by Xunta de Galicia (EM2013/041)
Period: Aug 2013 - Dec 2014
CELTIC: Strategic Knowledge led by technologies for the Competitive Intelligence
Funded by FEDER-INNTERCONECTA, CDTI, Imaxin Software
Period: Jan 2012 - Dec 2014
Evaluation and Optimization of the Locality of Irregular Applications on the SCC (Single-Chip Cloud Computer) Architecture
Funded by Intel Corporation  
Period: Oct 2009 - Oct 2012
OPTIMIZA: Optimization of Irregular Applications on High Performance CPU/GPU Emerging Architectures
Funded by Xunta de Galicia (PGIDIT09TIC002CT)
Period: Oct 2009 - Oct 2012
Using Hardware Counters to Improve Memory Performance: Irregular Codes and Page Migration
Funded by HP Labs  
Period: May 2008 - Apr 2011
Improving UPC Usability and Performance in Constellation Systems
Funded by HP Labs  
Period: May 2008 - Apr 2011

Contact

Juan Carlos Pichel
CITIUS (Universidade de Santiago de Compostela)
Rúa de Jenaro de la Fuente
15782 Santiago de Compostela (Spain)
juancarlos.pichel@usc.es
   +34 881816437