Javier Díaz Bruguera

ADDRESS

Centro de Investigación en Tecnoloxías da Información (CITIUS)
Campus Vida
Universidade de Santiago de Compostela
15782 Santiago de Compostela
Spain

e-mail: jd.bruguera@usc.es
Telephone: (+34) 881816452
Fax: (+34) 881816405

BIOGRAPHY

To see a brief biography follow this link

PROFESSIONAL SERVICES

Associated Editor in Chief (AEIC) of the IEEE Transactions on Computers since January 2015
Associated Editor (AE) of the IEEE Transactions on Computers since October 2010
Member Editorial Board of Advances in Computer Engineering, Hindawi Publishing Corporation, since June 2013
Member of the steering committee of the IEEE Symposium on Computer Arithmetic since 2009
Program co-chair of 19th IEEE Symposium on Computer Arithmetic (ARITH19, Portland, USA, June 2009)
Program co-chair of 8th Conference on Real Numbers and Computers (RNC8, Santiago de Compostela, Spain, July 2008)
Program co-chair of Europar 2008. Topic 10. Parallel numerical algorithms (2008)
Financial and Local Arrangements Chair of 16th IEEE Symposium on Computer Arithmetic (ARITH16, Santiago de Compostela, Spain, June 2003)

RESEACH

RESEARCH INTEREST

Computer arithmetic: floating-point arithmetic, algorithms and architectures, elementary functions, cryptography, accurate arithmetic, decimal arithmetic
Computer architecture: Transactional memory, functional units, manycore architectures

RESEARCH VISITOR

Department of Scientific Computation, University Pierre and Marie Curie (UPMC), París, France. July 5th - August 4th, 2013 (1 month)
Department of Electrical and Computer Engineering, University of California at Irvine, USA. July 1st - August 15th, 2004 (1.5 months)
Department of Electrical and Computer Engineering, University of California at Irvine, USA. July 1st - August 31th, 2001 (2 months)
Department of Electrical and Computer Engineering, University of California at Irvine, USA. July 1st - September 31th, 1999 (3 months)
Department of Electrical and Computer Engineering, University of California at Irvine, USA. July 1st - August 15th, 1997 (1.5 months)
Department of Electrical and Computer Engineering, University of California at Irvine, USA. October 5th, 1993 - December 20th, 1994 (15 months)
Application Center of Microelectronics (ACM) at Siemens, Munich, Germany. January 10th - June 2nd, 1993 (5.5 months)

PUBLICATIONS

This is a complete list of my research publications in chronological order. The list is split into journals and conference proceedings. Alternatively, you can see a similar list sorted into research topics in the publications section of the CITIUS. According google scholar, the h-index is 22 (14 since 2009), the i10-index is 50 (23 since 2009) and the total number of references is 1,668 (705 since 2009) (see the public profile).

JOURNALS

J.D. Bruguera. Optimizing the Representation of Intervals. Science of Computer Programming. Vol. 90 part A, pp. 21-33. September 2014.
A. Vázquez, E. Antelo and J.D. Bruguera. Fast radix-10 Multiplication Using Redundant BCD. IEEE Transactions on Computers. Vol. 63, No. 6, pp. 1902-1914. August 2014.
D. Piso and J.D. Bruguera. Obtaining Accurate Error Expressions and Bounds for Floating-Point Multiplicative Algorithms. The Computer Journal. Vol. 57, no. 2, pp. 319-331. February 2014.
X. Villar, D. Piso and J.D. Bruguera. FPGA Implementation of an Efficient Algorithm for the Calculation of Charged Particle Trajectories in Cosmic Ray Detectors. IEEE Transactions on Nuclear Science. Vol. 61, no. 1, pp. 590-595. February 2014
A. Vázquez and J.D. Bruguera. Iterative Algorithm and Architecture for Exponential, Logarithm, Powering and Root Extraction. IEEE Transactions on Computers. Vol. 62, no. 9, pp. 1721-1731, September 2013
R.R. Osorio and J.D. Bruguera. High-speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. Journal of Signal Processing Systems. Vol. 72, no. 2, pp. 119-132, August 2013
M. Daumas and J.D. Bruguera. Guest Editors’ Introduction Special Section on 8th Conference on Real Numbers and Computers. Information and Computation. Vol. 216, pp 1-2, July 2012
E.G. Paredes, M. Bóo, M. Amor, J.D. Bruguera and J. Döllner. Extended Hybrid Meshing Algorithm for Multiresolution Terrain Models. International Journal of Geographical Information Science. Vol. 26, No. 5, pp. 771-793. May 2012
50. L. Orosa, E. Antelo and J.D. Bruguera. FlexSig: Implementing Flexible Hardware Signatures. ACM Transactions on Architecture and Code Optimization. Special issue on High-Performance and Embedded Architectures and Compilers. Vol. 8, No. 4, pp. 30:1-30:20. January 2012
J.D. Bruguera, M. Cornea and D. Das Sarma. Guest Editors’ Introduction: Special Section on Computer Arithmetic. IEEE Transactions on Computers. Vol. 60, No. 2, pp. 145-147. February 2011
D. Piso and J.D. Bruguera. Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate. IEEE Transactions on Computers. Vol. 60, No. 11, pp. 1535-1546. November 2011
J.A. Piñeiro, J.D. Bruguera, F. Lamberti, P. Montuschi. A Radix-2 Digit-by-Digit Architecture for Cube Root. IEEE Transactions on Computers. Vol. 57, No. 4, pp. 562- 566. April 2008
P. Montuschi, J.D. Bruguera, L. Ciminiera, J.A. Piñeiro. A Digit-by-Digit Algorithm for m-th Root Extraction. IEEE Transactions on Computers. Vol. 56, No. 12, pp. 1696-1706. December 2007
F.J. Espino, M. Bóo, M. Amor and J.D. Bruguera. Hardware Support for Adaptive Tessellation of Bezier Surfaces Based on Local Tests. Journal of Systems Architecture. Vol. 53, No. 4, pp. 233-250. April 2007
R.R. Osorio and J.D. Bruguera. High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Transaction on Circuits and Systems for Video Technology. Vol. 16, No. 11, pp. 1376-1384. November 2006
J.A. Piñeiro, S. Oberman, J.-M Müller and J.D. Bruguera. High-Speed Function Approximation using a Minimax Quadratic Interpolator. IEEE Transactions on Computers. Vol. 54, No. 3, pp. 304-318. March 2005
J.A. Piñeiro, M.D. Ercegovac and J.D. Bruguera. High--Radix Logarithm with Selection by Rounding: Algorithm and Implementation. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology. Vol. 40, No. 1, pp. 109-123. 2005
J.A. Piñeiro, M.D. Ercegovac and J.D. Bruguera. Algorithm and Architecture for Logarithm, Exponential and Powering Computation. IEEE Transactions on Computers. Vol. 53, No. 9, pp. 1085-1096. September 2004
T. Lang and J.D. Bruguera. Floating-Point Multiply-Add Fused with Reduced Latency. IEEE Transactions on Computers. Vol. 53, No. 8, pp. 988-1003. August 2004
J.D. Bruguera and T. Lang. Multilevel Reverse-Carry Addition: Single and Dual Adders. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology. Vol. 33, No. 1-2, pp. 55-74. 2003
J. Touriño, J. Parapar, R. Doallo, M. Boullón, F.F. Rivera, J.D. Bruguera, X.P. González, R. Crecente, C. Álvarez. A GIS-embedded system to support land consolidation plans in Galicia. International Journal of Geographical Information Science. Vol. 17, No. 4, pp. 377-396. 2003
C. Álvarez, J. Touriño, F. F. Rivera, R. Crecente, X. P. González, R. Doallo, J. Parapar, J. D. Bruguera and M. Boullón. Automatización de los proyectos de concentración parcelaria. (In Spanish). Agricultura, revista agropecuaria. Pp. 46-51. 2003
D. Piso, J.A. Piñeiro and J.D. Bruguera. Analysis of the Impact of Different Methods for Division/Square root Computation in the Performance of Superscalar Microprocessor. Journal of Systems Architecture. Vol. 49, pp. 543-555. 2003
M. J. Martín, J. C. Mouriño, R. Doallo, D.E. Singh, F.F. Rivera and J.D. Bruguera. High Performance Air Pollution Modelling for a Power Plant Environment. Parallel Computing Journal. Vol. 29, No. 11-12, pp. 1763-1790. 2003
J.A. Piñeiro and J.D. Bruguera. High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. IEEE Transactions on Computers. Vol. 51, No. 12, pp. 1377-1388. December 2002
J.D. Bruguera and T. Lang. Multilevel Reverse Most-Significant-Carry Computation. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems. Vol. 9, No. 6, pp. 959-962. December 2001
E. Antelo, T. Lang and J.D. Bruguera. Very high radix circular CORDIC: vectoring and unified rotation/vectoring. IEEE Transactions on Computers. Vol. 47, No. 7, pp. 727-739. July 2000
E. Antelo, T. Lang and J.D. Bruguera. Very-High Radix CORDIC Rotation Based on Selection by Rounding. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology. Vol. 25, No. 2, pp. 141-153. 2000
J.D. Bruguera and T. Lang. Leading-One Prediction with Concurrent Position Correction. IEEE Transactions on Computers. Vol. 48, No. 10, pp. 1083-1097. October 1999
F. Argüello, M. Amor, M. Bóo and J.D. Bruguera. Algorithm for Wavelet Transform of Toeplitz Matrices. IEE Electronics Letter. Vol. 35, No. 10, pp. 775-776. May 1999
E. Antelo, M. Bóo, J.D. Bruguera and E.L. Zapata. Design of a Novel Circuit for Two Operand Normalization. IEEE Transactions on Very Large Scale of Integration Systems. Vol. 6, No. 1, pp. 173-176. March 1998
E. Antelo, T. Lang and J.D. Bruguera. Computation of sqrt(x/d) in a Combined Division/Square-Root Unit with Scaling and Selection by Rounding. IEEE Transactions on Computers. Vol. 47, No. 2, pp. 152-161. February 1998
M. Bóo, J.D. Bruguera and T. Lang. A VLSI Architecture for Arithmetic Coding of Multi-Level Images. IEEE Transactions on Circuits and Systems II. Vol. 45, No. 1, pp. 163-168. January 1998
J. Villalba, E. Antelo, J.D. Bruguera and E.L. Zapata. Radix-4 Vectoring CORDIC Algorithm and Architectures. Journal of VLSI Signal Processing. Vol. 19, No. 2, pp. 127-147. 1998.
E. Antelo, J.D. Bruguera, T. Lang and E.L. Zapata. Error Analysis and Reduction for Angle Calculation Using the Cordic Algorithm. IEEE Transactions on Computers. Vol. 46, No. 11, pp. 1264-1271. November 1997
E. Antelo, J. Villalba, J.D. Bruguera and E.L. Zapata. High Performance Rotation Architectures Based on Radix 4 CORDIC Algorithm. IEEE Transactions on Computers. Vol. 46, No. 8, pp. 855-870. August 1997
M. Bóo, F. Argüello, J.D. Bruguera, R. Doallo and E.L. Zapata. High--Performance VLSI Architecture for the Viterbi Algorithm. IEEE Transactions on Communications. Vol. 45, No. 2, pp. 168-176. February 1997
M. Bóo, F. Argüello, J.D. Bruguera and E.L. Zapata. Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. Journal of VLSI Signal Processing. Vol. 17, pp. 57-73. 1997
T.F. Pena, J.D. Bruguera and E.L. Zapata. Finite Element Resolution of the 3D Stationary Semiconductor Device Equations on Multiprocessors. Journal of Integrated Computer-Aided Engineering. Vol. 4, No. 1, pp. 66-77. 1997
J.D. Bruguera and T. Lang. Implementation of the FFT Butterfly with Carry Save Arithmetic. IEEE Transactions on Circuits and Systems II. Vol. 43, No. 10, pp. 717-723. October 1996
E. Antelo, J.D. Bruguera and E.L. Zapata. Unified Mixed Radix 2-4 Redundant Cordic Processor. IEEE Transactions on Computers. Vol. 45, No. 9, pp. 1068-1073. September 1996.
J.D. Bruguera, N. Guil, T. Lang, J. Villalba and E.L. Zapata. Cordic Based Parallel/Pipelined Architecture for the Hough Transform. Journal of VLSI Signal Processing. Vol. 12, No. 3, pp. 207-221. 1996
F. Argüello, J.D. Bruguera and E.L.Zapata. Parallel Architecture for the Self-Sorting FFT algorithm. Journal of Parallel and Distributed Computing. Vol. 31, pp. 88-97. 1995
F. Argüello, J.D. Bruguera, R. Doallo and E.L. Zapata. Parallel Architecture for Fast Transforms with Trigonometric Kernel. IEEE Transactions on Parallel and Distributed Systems. Vol. 5, No. 10, pp. 1091-1099. October 1994
J.D. Bruguera, J.C. Cabaleiro, T.F. Pena, O.G. Plata, F.F. Rivera and E.L. Zapata. Metodología de Partición de Algoritmos en Computadores Hipercubo. (In Spanish). Revista de Informática y Automática. Vol. 26, No. 2, pp. 3-10. 1993
J.D. Bruguera, E. Antelo and E.L. Zapata. Design of a Pipelined Radix 4 CORDIC Processor. Parallel Computing. Vol. 19, pp. 729-744. 1993
E.L. Zapata, J.I. Benavides, F.F. Rivera, J.D. Bruguera, T.F. Pena and J.M. Carazo. Image Reconstruction on Hypercube Computers: Application to Electron Microscopy. Journal Signal Processing. Vol. 27, pp. 51-64. 1992
E.L. Zapata and J.D. Bruguera. Modelling Failure Rate for Reliability Models. International Journal of Electronics. Vol. 70, No. 1, pp. 43-50. 1991
T.F. Pena, J.C. Cabaleiro, J.D. Bruguera and E.L. Zapata. Filtering with the Fast T Transform. IEE Electronics Letters. Vol. 26, No. 11, pp. 718-720. May 1990
F. Argüello, R. Doallo, J.D. Bruguera and E.L. Zapata. Transformada Rápida de Hartley Radix 4 en Computadores Hipercubo. (In Spanish). Revista de Informática y Automática. Vol. 23, No. 1, pp. 7-14. January 1990
E.L. Zapata, O.G. Plata F.F. Rivera, J.D. Bruguera, R. Doallo I. Benavides and F. Argüello. Software Tools for Multiprocessor Simulation and Programming. Journal on Cybernetics and Systems. Vol. 21, pp. 157-176. 1990
J.D. Bruguera, E.L. Zapata and O.G. Plata. A Reliability Model for Multiprocessor Networks with Degradable Nodes. Journal on Microprocessing and Microprogramming. Vol. 29, pp. 15-25. 1990
O. G. Plata, J. D. Bruguera, F. F. Rivera, R. Doallo and E. L. Zapata. ACLE, A Software Package for SIMD Computers Simulation. The Computer Journal. Vol. 33, No. 3, pp. 194-203. 1990
F.F. Rivera, R. Doallo, J.D. Bruguera, E.L. Zapata and R. Peskin. Gaussian Elimination with Pivoting into Hypercubes. Parallel Computing. Vol. 14, pp. 51-60. 1990
E.L. Zapata, F. Argüello, F.F. Rivera and J.D. Bruguera. Multidimensional Fast Hartley Transform into SIMD Computers. Journal on Microprocessing and Microprogramming. Vol. 29, pp. 121-134. 1990
I. Garcia, J.J. Merelo, J.D. Bruguera and E.L. Zapata. Parallel Quadrant Interlocking Factorization into Hypercube Computers. Parallel Computing. Vol. 15, pp. 87-100. 1990
E.L. Zapata, J.D. Bruguera, O.G. Plata and F.F Rivera. A Parallel Markovian Model Reliability Algorithm for Hypercube Computers. Journal on Microprocessing and Microprogramming. Vol. 27, pp. 501-508. 1989
F. Ríos, A. Fondado, I. Navarrina, J.D. Bruguera A. Docampo, R. Marín and J. Mira. Un Módulo de Laboratorio para el Análisis y Diseño de Funciones Electrónicas. (in Spanish) Revista de Informática y Automática. Vol. 17, pp. 18-21. 1984

CONFERENCES

D. Piso and J.D. Bruguera. A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms. Proc. 17th Euromicro Conference on Digital System Design. (DSD). Verona (Italy), pp. 639-642. 2014.
E.G. Paredes, M. Bóo, M. Amor, J. Döllner and J.D. Bruguera. GPU-Based Visualization of Hybrid Terrain Models. International Conference on Computer Graphics Theory and Applications (GRAPP 2012). Rome (Italy). pp. 254-259. 2012
J.D. Bruguera. Optimizing the Representation of Intervals. Invited speaker. Workshop on Numerical Software: Design, Analysis and Verification, Santander, Spain. 2012
A. Vázquez, J.D. Bruguera. Composite Iterative Algorithm and Architecture for q-th Root Calculation. IEEE 20th Symp. Computer Arithmetic. (ARITH20). Tubingen (Germany). pp. 52-61. 2011
D. Piso and J.D Bruguera. Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Calculation. Proc. 12th Euromicro Conference on Digital System Design. (DSD'2009). Patras (Greece). pp. 293-300. 2009
C. Díaz Resco, R.R.Osorio and J.D. Bruguera. High Performance Image Processing on a Massively Parallel Processor. Proc. 12th Euromicro Conference on Digital System Design. (DSD'2009). Patras (Greece). pp. 233- 236. 2009
D. Piso and J.D. Bruguera. Simplifying the Rounding for Newton-Raphson Algorithm with Parallel Remainder Calculation. 43th Annual Asilomar Conference on Signals, Systems, and Computers. Track on Architectures and Implementations. Monterrey (USA). 2009
L. Orosa, J.D. Bruguera and E. Antelo. A Cache Filtering Mechanism for Hardware Transactional Memory Systems Decoupled from Caches. XX Jornadas de Paralelismo, A Coruña (Spain). pp. 165-170. 2009
R.R. Osorio, C. Díaz-Resco and J.D. Bruguera. Highly Parallel Image Processing on a Massively Parallel Processor Array. XX Jornadas de Paralelismo, A Coruña (Spain). pp. 283-288. 2009.
R.R. Osorio and J.D. Bruguera. An FPGA Architecture for CABAC Decoding in Many-core Systems. IEEE 19th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2008). Leuven (Belgium). pp. 293.298. 2008
D.Piso and J.D. Bruguera. A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. Proc. 11th Euromicro Conference on Digital System Design. (DSD'2008). pp. 760-767. Parma, Italy, pp. 760-767. 2008
D.Piso and J.D. Bruguera. Forcing one-sided results in Goldschmidt algorithm. 42th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, USA. pp. 1830-1833. 2008
T. Lang and J.D. Bruguera. A Hardware Error Estimate for Floating—Point Computations. Proc. SPIE Conference. Advanced Signal Processing Algorithms, Architectures and Implementations XVIII. San Diego, USA. pp. 70740N1-70740N11. 2008
R.R. Osorio and J.D. Bruguera. Entropy Coding on a Programmable Processor Array for Multimedia SOC. IEEE 18th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007). Montreal (Canada). pp. 222-227. 2007
V. Holimath and J. D. Bruguera. A Linear Convergent Functional Iterative Division Without Look-Up Table. 9th Euromicro Conference on Digital System Design (DSD'2006). pp. 236-239. Dubrovnik (Croatia). 2006
R.R.Osorio and J.D. Bruguera. A Combined memory Compression and Hierarchical Motion Estimation Architecture for Video Encoding in Embedded Systems. 9th Euromicro Conference on Digital System Design (DSD'2006). Dubrovnik (Croatia). 2006
J.D. Bruguera and R.R Osorio. An Unified Architecture for H.264 Multiple Block--Size DCT with Fast and Low Cost Quantization. 9th Euromicro Conference on Digital System Design (DSD'2006). Dubrovnik (Croatia). 2006
T. Lang and J.D. Bruguera. The Sunity Representation to Improve the Accuracy of Some Computations. 7th Conference on Real Numbers and Computers (RNC7). Nancy (France). 2006
D. Piso and J.D. Bruguera. Optimizing the Multiplier Desing for Goldschmidts Division and Reciprocal Units. XXI Conference on Design of Circuits and Integrated Systems (DCIS2006). Barcelona (Spain). pp. 2006
M.E. Castro, R.R. Osorio and J.D. Bruguera. Optimizing CABAC for VLIW architectures. XXI Conference on Design of Circuits and Integrated Systems (DCIS2006). Barcelona (Spain). 2006
F.J. Espino, M. Bóo, M. Amor and J.D. Bruguera. Adaptive Tessellation Of Bezier Surfaces Based On Displacement Maps. 13th Int. Conf. In Central Europe on Computer Graphics, Visualization and Computer Vision (WSCG'2005). Plzen (Czech Republic)). 2005
J.D. Bruguera, T. Lang. Floating-Point Multiply-Add Fused: Latency Reduction for Floating-Point Addition. IEEE 17th Symp. Computer Arithmetic. (ARITH17). Cape Cod (USA). 2005
R.R. Osorio and J.D. Bruguera. A New Architecture for Fast Arithmetic Coding in H.264 Advanced Video Coder. Euromicro Symposium on Digital System Design (DSD'2005). Porto (Portugal). 2005
F.J. Espino, M. Bóo, M. Amor and J.D. Bruguera. Hardware Support for Adaptive Tessellation of Bézier Surfaces with Combined Tests. XX Conference on Design of Circuits and Integrated Systems (DCIS2005). Lisboa (Portugal). 2005
T. Lang and J.D. Bruguera. Representation of Unit range numbers. 39th Annual Asilomar Conference on Signals, Systems, and Computers. Track on Architectures and Implementations. Monterrey (USA). 2005
D. Piso and J.D. Bruguera. Error Analysis of Goldschmidt Algorithm. Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2005). pp. 295-298. L’Aquila (Italy). 2005
P.N. Mallón, M. Bóo, M. Amor and J.D. Bruguera. Algorithms and Hardware for Data Compression in Point Rendering Applications. 12th Int. Conf. In Central Europe on Computer Graphics, Visualization and Computer Vision (WSCG'2004). pp.173-180. Plzen (Czech Republic). 2004
P.N. Mallón, M. Bóo, M. Amor and J.D. Bruguera. Compression and On--the--Fly Rendering Using Tetrahedal Concentric Strips. Euromicro Symposium on Digital System Design (DSD'2004), Work in progress Session. Rennes (France). 2004
F.J. Espino, M. Bóo, M. Amor and J.D. Bruguera. Adaptive Tessellation of Bézier Surfaces Based on Distance Maps and Local Tests. Euromicro Symposium on Digital System Design (DSD'2004), Work in progress Session. Rennes (France). 2004
R. R. Osorio and J.D. Bruguera. Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. Euromicro Symposium on Digital System Design (DSD'2004). Rennes (France). 2004
J.A. Piñeiro, J.D. Bruguera. On--Line High-Radix Exponential with Selection by Rounding. IEEE International Symposium on Circuits and Systems (ISCAS2003). Bangkok (Thailand). 2003
J.A. Piñeiro, J.D. Bruguera and M. Ercegovac. High Radix Iterative Algorithm for Powering Computation. IEEE 16th Symp. Computer Arithmetic (ARITH16). Santiago de Compostela (Spain). 2003
J. Espino, M. Bóo, M. Amor and J.D. Bruguera. Adaptive Tessellation of NURBS Surfaces. 11th Int. Conf. In Central Europe on Computer Graphics, Visualization and Computer Vision (WSCG'2003). Plzen (Czech Republic). 2003
J.A. Piñeiro, M.D. Ercegovac and J.D. Bruguera. High—Radix Logarithm with Selection by Rounding. IEEE 13th Int. Conf. on Application-Specific Systems, Architectures and Processors. ASAP 2002. San Jose (USA). pp. 101-110. 2002
P.N. Mallón, M. Bóo and J.D. Bruguera. Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. IEEE Conf. on 3D Data Processing, Visualization and Transmission. 3DPVT'2002. pp. 380-383. Padua (Italy). 2002
A. del Rio, M. Boo, M. Amor, J.D. Bruguera. Hardware Implementation of the Subdivision Loop Algorithm. 28th Euromicro Conf. Multimedia and Telecommunications Track. Dortmund (Germany). 2002
J. Espino, M. Bóo and J.D. Bruguera. Implementation of a Modified Bezier Clipping Algorithm in a Superscalar Architecture. XVII Conference on Design of Circuits and Integrated Systems (DCIS-2002). Santander (Spain). 2002
J.A. Piñeiro, M.D. Ercegovac and J.D. Bruguera. Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. Int. Conf. Computer Design. ICCD'2002. Freiburg (Germany ). 2002
T. Lang and J.D. Bruguera. Floating--Point Fused Multiply--Add with Reduced Latency. Int. Conf. Computer Design. ICCD'2002. Freiburg (Germany). 2002
D. Piso, J.A. Piñeiro and J.D. Bruguera. Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. Euromicro Symposium on Digital System Design (DSD'2002). pp. 218-225. Dortmund (Germany). 2002
M. Bóo, J.D. Bruguera and E.L. Zapata. Architectures for Bézier Clipping Algorithm. IS & T/SPIE 13th Int. Symp. Electronic Imaging 2001. Media Processors 2001. San José (USA). 2001
J.A.Piñeiro, J.D. Bruguera and J.M. Muller. Faithful Powering Computation using Table Look-up and Fussed Accumulation Tree. IEEE Symp. 15th Computer Arithmetic. ARITH15. Vail (USA). 2001
J.D. Bruguera and T. Lang. Double-Datapath Floating-Point Adder using the Reverse-Carry Approach. IEEE Symp. 15th Computer Arithmetic. ARITH15. Vail (USA). 2001
J. Touriño, F.F. Rivera, C. Alvarez, C.M. Dans, J. Parapar, R. Doallo, M. Boullóu, J.D. Bruguera, R. Crecente and X. P. González. COPA. A GIS based tool for land consolidation projects. 9th ACM Int. Symp. on Advances in Geographic Information Systems. ACM-GIS 2001. Atlanta (USA). 2001
J. C. Mouriño, D. E. Singh, M. J. Martín, F. F. Rivera, R. Doallo and J. D. Bruguera. The STEM-II Air Quality Model on a Distributed Memory System. Workshop on High Performance Scientific and Engineering computing with Applications (HPSECA-2001) in conjunction with the International Conference on Parallel Processing (ICPP-2001). Valencia (Spain). 2001
J. C. Mouriño, D. E. Singh, M. J. Martín, J.M. Eiroa, F. F. Rivera, R. Doallo and J. D. Bruguera. Parallelization of the STEM-II Air Quality Model. Int. Symp. High Performance Computing and Networking (HPCN2001). Amsterdam (The Netherlands). 2001
M. Bóo, J.D. Bruguera and E.L. Zapata. Architecture for Bézier clipping algorithm. IS&T/SPIE 13th Int. Symp. Electronic Imaging 2001. Media Processors 2001. San Jose (USA). 2001
P.N. Mallón, M. Bóo and J.D. Bruguera. Implementation of a NURBS to Bézier conversor with constant latency. 11th International Conference on Field Programmable Logic and Applications, (FPL2001). pp. 213-222. Belfast (UK). 2001
P.N. Mallón, M. Bóo and J.D. Bruguera. Minimun latency for NURBS to Bézier converter. XVI Conf. Design of Circuits and Integrated Systems, DCIS'01. pp. 230-235. Porto (Portugal). 2001
J.A. Piñeiro and J.D. Bruguera. High-Speed Double-Precision Computation of Reciprocation and Division. XVI Conf. Design of Circuits and Integrated Systems, DCIS'01. Porto (Portugal). 2001
J.A. Piñeiro, J.D. Bruguera and J.M. Muller. FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. EUROMICRO Symposium on Digital System Design (DSD'2001). Warsaw (Poland). 2001
M. Bóo, J.D. Bruguera and E.L. Zapata. Parallel Architecture for the Computation of NURBS Surfaces. IS & T/SPIE 12th Int. Symp. Electronic Imaging 2000. Media Processors 2000. San José (USA). 2000
R.R. Osorio and J.D. Bruguera. Architectures for Arithmetic Coding in Image Compression. X European Signal Processing Conference, EUSIPCO 2000. Tampere (Finlandia). 2000
C. Cabrera and J.D. Bruguera. VLSI systolic array architecture for the lattice structure of the Discrete Wavelet Transform. Int. Conf. on Circuits and Systems, ISCAS2000. Genève (Switzerland). 2000
D.E. Singh, M.Arenaz, F.F. Rivera, J.D. Bruguera, J. Touriño, R. Doallo, M.R. Mendez, J.A. Souto and J. Casares. Some proposals about the vector and parallel implementations of STEM-II. 8th Int. Conf. Development and Application of Computer Techniques to Environmental Studies. ENVIROSOFT 2000. Bilbao (Spain). 2000
J.D. Bruguera and T. Lang. Multilevel reverse-Carry Adder. Int. Conf. Computer Design. ICCD'2000. Austin (USA). 2000
P.N. Mallón, M. Bóo and J.D. Bruguera. Parallel Architectures for Conversion of NURBS Curves to Bézier Curves. Int. Conf. Euromicro2000. Worshop Digital System Design (DSD2000). pp. 324-331. Maastricht (The Netherlands). 2000
J.C. Mouriño, D.E. Singh, M. Arenaz, M.J. Martín, F.F. Rivera, R. Doallo and J.D. Bruguera. Implementación de Modelo de Dispersión Fotoquímica STEM-II sobre Sistemas Distribuidos. Simposio Español de Informática Distribuida. SEID2000. Ourense (Spain). 2000
E. Antelo, T. Lang and J.D. Bruguera. Very--High Radix CORDIC Vectoring Based on Pre--Scaling and Selection by Rounding. IEEE 14th Symp. Computer Arithmetic. Adelaida (Australia). 1999
R.R. Osorio and J.D. Bruguera. New Model for Arithmetic Coding/Decoding of Multilevel Images Based on a Cache Memory. Int. Conf. on Electronics, Circuits and Systems (ICECS'99). Cyprus. 1999
T. Lang and J.D. Bruguera. Multilevel Reverse\Carry Computation for Comparison and for Sign and Overflow Detection in Addition. Int. Conf. Computer Design. ICCD'99. Austin (USA). 1999
J.A. Piñeiro, E. Antelo and J.D. Bruguera. Circuit Implementation of a Very High Radix Cordic Vectoring Algorithm for Angle Calculation. XII Conf. Design of Integrated Circuits and Systems. DCIS'99. Palma de Mallorca (Spain). 1999
R.R. Osorio, M. Bóo and J.D. Bruguera. Arithmetic Coding/Decoding Architecture Based on a Cache Memory. Int Conf. Euromicro'98. Vasteras (Sweden). 1998
J.D. Bruguera and T. Lang. Leading--One Prediction Scheme for Latency Improvement in Single Datapath Floating—Point Adders. Int. Conf. Computer Design. ICCD'98. Austin (USA). 1998
J. Salceda, R. Doallo and J.D. Bruguera. Technology Independent Power estimation in CMOS Integrated Circuits. XI Conf. Design of Integrated Circuits and Systems. DCIS'98. Madrid (Spain). 1998
C. Cambrera, M. Bóo and J.D. Bruguera. VLSI Implementation of an Area--Efficient Architecture for the Viterbi Algorithm. Int. Conf. Acoustics, Speech and Signal Processing, ICASSP'97. Munich (Germany). 1997
M. Peón, R.R. Osorio and J.D. Bruguera. A VLSI Implementation of an Arithmetic Coder for Image Compression. Int. Conf. Euromicro—97. Budapest (Hungary). 1997<7Li>
R.R. Osorio and J.D. Bruguera. New Arithmetic Coder/Decoder Architectures Based on Pipelining. Int. Conf. Application Specific Array Processors. ASAP'97. Zurich (Switzerland). 1997
J.M. Calo, E. Antelo and J.D. Bruguera. VLSI Implementation of an Architecture for Angle Computation and Rotation. X Conf. Design of Integrated Circuits and Systems. DCIS'97. Sevilla (Spain)). 1997
M. Bóo and J.D. Bruguera. Pipelined Architectures for the Viterbi Algorithm. Int. Conf. TENCON'97. Brisbane (Autralia). 1997
J. Villalba, J.C. Arrabal, E. Antelo, J.D. Bruguera and E.L. Zapata. Radix--4 Vectoring CORDIC Algorithms and Architectures. Proc. Int. Conf. Application Specific Array Processors. ASAP'96. Chicago (USA). 1996
M. Bóo, F. Argüello and J.D. Bruguera. High—Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. Proc. Int. Conf. Application Specific Array Processors. ASAP'96. Chicago (USA). 1996
M. Bóo, F. Argüello J.D. Bruguera and E.L. Zapata. High--Performance VLSI Architecture for the Trellis Coded Quantization. Int. Conf. on Image Processing. ICIP'96. Lausanne (Switzerland). 1996
L. Costas, E. Antelo, M. Bóo and J.D. Bruguera. Implementación VLSI de una Nueva Arquitectura de Normalización. XI Conf. Design of Integrated Circuits and Systems. DCIS'96. Sitges (Spain). 1996
E. Antelo, J.D. Bruguera, T. Lang, J. Villalba and E.L. Zapata. High Radix CORDIC Rotation based on Selection by Rounding. Parallel Processing. Lyon (France). 1995
E. Antelo, M. Bóo, J.D. Bruguera and T. Lang. Diseño e Implementación de un circuito integrado VLSI para la 2-D DCT con aritmética on—line. X Congreso de Diseño de Circuitos Integrados. Zaragoza (Spain). 1995
M. Sánchez, J.D. Bruguera and E.L. Zapata. Arquitectura Semisistólica para el Procesado de la DCT. X Congreso de Diseño de Circuitos Integrados. Zaragoza (Spain). 1995
J.D. Bruguera and T. Lang. 2-D DCT Using On—Line Arithmetic. IEEE Int. Conf. Acoustics, Speech and Signal Processing. ICASSP'95. Detroit (USA). 1995
Osorio, E. Antelo, J. Villalba, J.D. Bruguera and E.L.Zapata. Digit On--Line Large Radix Cordic Rotator. Int. Conf. Application Specific Array Processors. ASAP'95. Strasbourg (Frane). 1995
J. Villalba, J.A Hidalgo, E. Antelo, J.D. Bruguera and E.L. Zapata. Cordic Architectures with Parallel Compensation of the Scale Factor. Int. Conf. Application Specific Array Processors. ASAP'95. Strasbourg (France). 1995
E. Antelo, J.D. Bruguera and E.L. Zapata. Redundant CORDIC Rotator based on Parallel Prediction. IEEE 12th Symp. Computer Arithmetic. Bath (UK). 1995
M. Sánchez, J.D. Bruguera and E.L. Zapata. Bit Serial Architecture for the Calculation of the Two Dimensional DCT. 21st European Solid-State Circuits Conference. ESSCIRC—95. Lille (France). 1995
M. Sánchez, J.D. Bruguera and E.L. Zapata. Bit Serial Architecture for the Two Dimensional DCT. Int. Conf. on Signal Processing, Applications and Technology. ICSPAT'95.Boston (USA). 1995
M. Bóo, E. Antelo and J.D. Bruguera. Implementación del Operador de Sobel en un Circuito Integrado de Aplicación Específica. IX Congreso de Diseño de Circuitos Integrados. Las Palmas (Spain). 1994

Un Nuevo Metodo Iterativo para la Resolución de la Ecuación de Poisson no Lineal en el Proceso de Simulacion 3D de Semiconductores

M. Bóo, E. Antelo and J.D. Bruguera. VLSI Implementation of an Edge Detector Based on Sobel Operator. Euromicro-94. Liverpool (UK). 1994
E. Antelo, J.D. Bruguera and E.L.Zapata. Unnormalized Fixed Point Cordic Arithmetic for SVD Processors. Int. Conf. on Signal Processing, Applications and Technology. ICSPAT'94. Dallas (USA). 1994
I. Aldea, E. Antelo and J.D. Bruguera. Diseño e Implementación VLSI de un Procesador CORDIC Radix 4 para Procesado Digital de Señales. VIII Congreso de Diseño de Circuitos Integrados. Málaga (Spain). 1993
F. Argüello, V. Armas, J. Bautista, J.D. Bruguera, R. Sarmiento and E.L. Zapata. Procesador FFT. Parte I: Sección de Control. VIII Congreso de Diseño de Circuitos Integrados. Málaga (Spain). 1993
F. Argüello, V. Armas, J. Bautista, J.D. Bruguera, R. Sarmiento and E.L. Zapata. Procesador FFT. Parte II: Sección de Procesamiento Basada en Cordic. VIII Congreso de Diseño de Circuitos Integrados. Málaga (Spain). 1993
E. Antelo, J.D. Bruguera and E.L. Zapata. Diseño de un Procesador CORDIC para la Implementación de Funciones no Lineales. VII Congreso de Diseño de Circuitos Integrados. Toledo (Spain). 1992
E.L. Zapata, J.I.Benavides, J.D. Bruguera and J.M Carazo. Image Reconstruction on Transputer Networks. Aplication of Transputers. Southamptom (UK). 1992
R. Doallo, F. Argüello, J.D. Bruguera and E.L. Zapata. Diseño de un Procesador para la Identificación de Patrones. VI Jornadas de Diseño de Circuitos Integrados. Santander (Spain). 1991
F. Argüello, R. Doallo, J.D. Bruguera and E.L. Zapata. Design of a Constant Geometry Fast Hartley Transformer. IEEE Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP'91). Toronto (Canada). 1991
E.L. Zapata, F. Argüello and J.D. Bruguera. A Constant Geometry Semisystolic Architecture for Fast Hartley Transform. IEEE CompEuro 91 Conference. Bologna (Italy). 1991
E. L. Zapata, J. I. Benavides, J. D. Bruguera, O. G. Plata and F.F. Rivera. Algoritmos Numéricos en Computadores Hipercubo. I Cong. sobre Métodos Numéricos en Ingeniería. Las Palmas (Spain). 1990
J.I. Benavides, T.F. Pena, E.L. Zapata, J.M. Carazo and J.D.Bruguera. Filtered Back Projection on Hypercube Computers. Parallel Computing in Engineering and Engineering Education. Paris (France). 1990
E.L. Zapata, J.I. Benavides, J.D. Bruguera and J.M. Carazo. Image Reconstruction on Hypercube Computers.IEEE Frontiers'90. Frontiers of Massively Parallel Computation. Maryland (USA). 1990
J.D. Bruguera and E.L. Zapata. VLSI Multiprocessor Reliability: Influence of Yield. 12th Int. Conf. on Fault-Tolerant Systems and Diagnostics. Prague (Czech Repulic). 1989
J.D. Bruguera and E.L. Zapata. Markov Reliability Model Based on the Residual Function of the Nodes. IFAC Int.Symp. on Low Cost Automation. Milan (Italy). 1989
J. D. Bruguera, E. L. Zapata, O. G. Plata and F. F. Rivera. A Parallel Planar Graphs Separator Cycle Algorithm for Hypercube Computers. 2th Int. Symp. on System Researchs, Informatics and Cybernetics. Baden-Baden (Germany). 1989
O. G. Plata, F. Argüello, J. D. Bruguera and E. L. Zapata. An Array Processing Language for Real Time Programming of Hypercube Concurrent Computers. IEE Sec. Int. Conf. on Software Engineering for Real Time Systems. Cirencester (UK). 1989
E.L. Zapata and J.D. Bruguera. A Reliability Model for Multiprocessor System with Planar Topology and Degradable Nodes. 1th Int. Symp. on System Researchs, Informatics and Cybernetics. Baden-Baden (Germany). 1988
E.L. Zapata, J.D. Bruguera and J. Mira. Design of a Multigate Resource Fault Tolerant Controller. 29th ISMM Int.Symp. MIMI'85. Mini and Microcomputers and their Applications. Sant Feliu de Guixols (Spain). 1985
J.D. Bruguera, E.L. Zapata and J. Mira. Árbitro de Recursos Compartidos Multipuerta. V Reunión del GEM. Sevilla (Spain). 1984

FUNDED RESEARCH PROJECTS

This is a list of the funded projects I have been participating as responsible of the project

Hardware and Software Techniques for High Performance Computing (SHSCAP). Supported by Ministry of Economy and Competitiveness, co-funded by the FEDER funds of the European Union, under contract TIN2013-41129-P (2014 - 2017)
Hardware and Software for High Performance Computing (HSCAP). Supported by Ministry of Science and Innovation of Spain, co-funded by the FEDER funds of the European Union, under contract TIN2010-17541 (01/01/2011 - 31/12/2014)
Hardware and Software Support for High Performance Computing (HSHPC). Supported by Ministry of Science and Innovation of Spain, co-funded by the FEDER funds of the European Union, under contract TIN2007-67537-C03 (01/10/2007-31/03/2011)
Middleware and Hardware Solutions in High Performance Computing: Focus on Multimedia and Simulation Applications. Supported by Ministry of Education and Science of Spain, co-funded by the FEDER funds of the European Union, under contract TIN2004-07797-C02 (13/12/2004-12/06/2008)
High Performance Computing for Rendering: Exploiting the Hierarchy Memory and Mapping of Algorithms on Hardware. Supported by Ministry of Education and Science of Spain, co-funded by the FEDER funds of the European Union, under contract TIN2001-3694-C02 (28/12/2001-27/12/2004)
High Performance Graphics Computing: Design of Architectures and Parallelization on Supercomputers. Supported by the Office of Research and Development of Galicia, Spain, under contract PGIDT99-PXI20602B (01/01/1999-31/12/2001)
Modelling the Dispersion and Chemical Transformation of Atmospheric Pollutans on Supercomputers for the Determination and Application of Strategies for the Emision Reductions in the Power Plant of As Pontes, Spain. Supported by Ministry of Education and Science of Spain, co-funded by the FEDER funds of the European Union, under contract 1FD97-0118-C02 (01/11/1998-30/10/2001)
Architectures and Parallelization on High Performance Computing: Dynamic and/or Sparse-Matrix Based Applications. Supported by Ministry of Education and Science of Spain, co-funded by the FEDER funds of the European Union, under contract TIC96-1125-C03-02 (01/08/1996-31/07/1999)
Design and Development of Application Specific VLSI Architectures for Image Compression. Supported by the Office of Research and Development of Galicia, Spain, under contract XUGA20605B95 (1996-1997)
Massively Parallel Computing: Design of VLSI Architectures. Supported by Ministry of Education and Science of Spain, co-funded by the FEDER funds of the European Union, under contract TIC92-0942-C03-03 (1993-1995)
Design of Application Specific Integrated Cicuits for Image Processing. Supported by the Office of Research and Development of Galicia, Spain, under contract XUGA 20601A91 (1992-1993)

PhD THESIS

Lois Orosa Nogueira. New Hardware Support for Transactional Memory and Parallel Debugging in Multicore Processors. University of Santiago de Compostela. September 20th, 2013
Daniel Piso Fernández. Improving Variable-Latency Algorithms for the Calculation of Division, Square Root and its Reciprocals. (In Spanish). University of Santiago de Compostela. Novembre 20th, 2009
Vijaykumar Holimath. Division and Square Root for Mobile and Scientific Computing Markets. University of Santiago de Compostela. December 19th, 2007
Paula Novío Mallón. Software/Hardware Techniques for Mesh Compression in Computer Graphics. University of Santiago de Compostela. 2006
José Alejandro Piñeiro Riobó. Algorithms and Architectures for Elementary Function Computation. University of Santiago de Compostela. 2003
Roberto Rodríguez Osorio. Algorithms and Architectures fro Arithmetic Coding: Exploiting the Locality Using Cache Memories. (In Spanish). University of Santiago de Compostela. 1999
Carlos Fernández Sánchez. Analysis of the Climatic Sensitivity in the Community Climate Model. (In Spanish). University of Santiago de Compostela. 1999
Monserrat Bóo Cepeda. Mapping of the Viterbi Algorithm on Area-Efficient VLSI Architectures. (In Spanish). University of Santiago de Compostela. 1997
Elisardo Antelo Suárez. Redundant Arithmetic CORDIC Algorithms and Architectures for High-Speed Processing. (In Spanish). University of Santiago de Compostela. 1995
Tomás Fernández Pena. 3D Simulation of Semiconductor Devices in Multiprocessor Systems. (In Spanish). University of Santiago de Compostela. 1994